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» A Dynamic Multithreading Processor
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SIGARCH
2008
97views more  SIGARCH 2008»
13 years 8 months ago
SP-NUCA: a cost effective dynamic non-uniform cache architecture
1 This paper presents a simple but effective method to reduce on-chip access latency and improve core isolation in CMP Non-Uniform Cache Architectures (NUCA). The paper introduces ...
Javier Merino, Valentin Puente, Pablo Prieto, Jos&...
HPDC
2012
IEEE
11 years 11 months ago
Dynamic adaptive virtual core mapping to improve power, energy, and performance in multi-socket multicores
Consider a multithreaded parallel application running inside a multicore virtual machine context that is itself hosted on a multi-socket multicore physical machine. How should the...
Chang Bae, Lei Xia, Peter A. Dinda, John R. Lange
ICS
2009
Tsinghua U.
14 years 1 months ago
Dynamic task set partitioning based on balancing memory requirements to reduce power consumption
ABSTRACT Because of technology advances power consumption has emerged up as an important design issue in modern high-performance microprocessors. As a consequence, research on redu...
Diana Bautista, Julio Sahuquillo, Houcine Hassan, ...
ISVLSI
2005
IEEE
157views VLSI» more  ISVLSI 2005»
14 years 2 months ago
Configurable Multiprocessors for High-Performance MPEG-4 Video Coding
We investigate the performance improvement of a multithreaded MPEG-4 video encoder executing on a configurable, extensible, SoC multiprocessor. Architecture-level results indicate...
Vassilios A. Chouliaras, Tom R. Jacobs, Ashwin K. ...
MASCOTS
2004
13 years 10 months ago
Simulation Evaluation of Hybrid SRPT Scheduling Policies
This paper uses trace-driven simulations to evaluate two novel Web server scheduling policies called KSRPT and T-SRPT. K-SRPT is a multi-threaded version of SRPT (Shortest Remaini...
Mingwei Gong, Carey L. Williamson