1834 search results - page 84 / 367 » A Dynamic Multithreading Processor |
MICRO
1998
IEEE
14 years 2 months ago
1998
IEEE
This paper provides quantitative measurements of load latency tolerance in a dynamically scheduled processor. To determine the latency tolerance of each memory load operation, our...
ISCA
2003
IEEE
14 years 3 months ago
2003
IEEE
Clustered microarchitectures are an attractive alternative to large monolithic superscalar designs due to their potential for higher clock rates in the face of increasingly wire-d...
LCN
2002
IEEE
14 years 3 months ago
2002
IEEE
The combination of high-performance processing power and flexibility found in network processors (NPs) has made them a good solution for today’s packet processing needs. Similar...
FPL
2008
Springer
13 years 11 months ago
2008
Springer
In multi-context Dynamically Reconfigurable Processor Array (DRPA), the required number of contexts is often increased by those with low resource usage. In order to execute such c...
FPL
2008
Springer
13 years 11 months ago
2008
Springer
The power consumption of Dynamically Reconfigurable Processing Array (DRPA) is quantitatively analyzed by using a real chip layout and applications taking into account the reconfi...