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ASPDAC
2012
ACM
253views Hardware» more  ASPDAC 2012»
13 years 10 months ago
An integrated and automated memory optimization flow for FPGA behavioral synthesis
Behavioral synthesis tools have made significant progress in compiling high-level programs into register-transfer level (RTL) specifications. But manually rewriting code is still ...
Yuxin Wang, Peng Zhang, Xu Cheng, Jason Cong
DAC
2009
ACM
15 years 7 months ago
Heterogeneous code cache: using scratchpad and main memory in dynamic binary translators
Dynamic binary translation (DBT) can be used to address important issues in embedded systems. DBT systems store translated code in a software-managed code cache. Unlike general-pu...
José Baiocchi, Bruce R. Childers
DAC
2001
ACM
16 years 3 months ago
Improved Cut Sequences for Partitioning Based Placement
Recursive partitioning based placement has a long history, but there has been little consensus on how cut sequences should be chosen. In this paper, we present a dynamic programmi...
Mehmet Can Yildiz, Patrick H. Madden
TII
2010
166views Education» more  TII 2010»
14 years 9 months ago
Source-to-Source Architecture Transformation for Performance Optimization in BIP
Behavior, Interaction, Priorities (BIP) is a component framework for constructing systems from a set of atomic components by using two kinds of composition operators: interactions ...
Marius Bozga, Mohamad Jaber, Joseph Sifakis
HIPEAC
2005
Springer
15 years 7 months ago
A Practical Method for Quickly Evaluating Program Optimizations
This article aims at making iterative optimization practical and usable by speeding up the evaluation of a large range of optimizations. Instead of using a full run to evaluate a s...
Grigori Fursin, Albert Cohen, Michael F. P. O'Boyl...