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ENTCS
2002
166views more  ENTCS 2002»
13 years 10 months ago
Translation and Run-Time Validation of Optimized Code
The paper presents approaches to the validation of optimizing compilers. The emphasis is on aggressive and architecture-targeted optimizations which try to obtain the highest perf...
Lenore D. Zuck, Amir Pnueli, Yi Fang, Benjamin Gol...
ISPD
2012
ACM
288views Hardware» more  ISPD 2012»
12 years 6 months ago
Construction of realistic gate sizing benchmarks with known optimal solutions
Gate sizing in VLSI design is a widely-used method for power or area recovery subject to timing constraints. Several previous works have proposed gate sizing heuristics for power ...
Andrew B. Kahng, Seokhyeong Kang
UML
2000
Springer
14 years 2 months ago
Using UML Collaboration Diagrams for Static Checking and Test Generation
Software testing can only be formalized and quanti ed when a solid basis for test generation can be de ned. Tests are commonly generated from program source code, graphical models ...
Aynur Abdurazik, A. Jefferson Offutt
ISCAS
2006
IEEE
106views Hardware» more  ISCAS 2006»
14 years 4 months ago
An efficient SNR scalability coding framework hybrid open-close loop FGS coding
Abstract—This paper presents a novel high-efficient hybrid openclose loop based fine granularity scalable (HOCFGS) coding framework supporting different decoding complexity appli...
Xiangyang Ji, Debin Zhao, Wen Gao, Jizheng Xu, Fen...
DAC
2005
ACM
14 years 11 months ago
Memory access optimization through combined code scheduling, memory allocation, and array binding in embedded system design
In many of embedded systems, particularly for those with high data computations, the delay of memory access is one of the major bottlenecks in the system's performance. It ha...
Jungeun Kim, Taewhan Kim