90 search results - page 5 / 18 » A Dynamically Adaptable Hardware Transactional Memory |
ISCA
2010
IEEE
14 years 21 days ago
2010
IEEE
Next generation tiled microarchitectures are going to be limited by off-chip misses and by on-chip network usage. Furthermore, these platforms will run an heterogeneous mix of ap...
ICAC
2007
IEEE
14 years 1 months ago
2007
IEEE
— The multi-tier implementation has become the industry standard for developing scalable client-server enterprise applications. Since these applications are performance sensitive...
PDP
2010
IEEE
13 years 12 months ago
2010
IEEE
The increasing numbers of cores, shared caches and memory nodes within machines introduces a complex hardware topology. High-performance computing applications now have to carefull...
VEE
2006
ACM
14 years 1 months ago
2006
ACM
During recent years, microprocessor energy consumption has been surging and efforts to reduce power and energy have received a lot of attention. At the same time, virtual executio...
ISCA
1997
IEEE
13 years 11 months ago
1997
IEEE
Improvements in main memory speeds have not kept pace with increasing processor clock frequency and improved exploitation of instruction-level parallelism. Consequently, the gap b...