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FCCM
2007
IEEE
168views VLSI» more  FCCM 2007»
13 years 7 months ago
Discrete-Time Cellular Neural Networks in FPGA
This paper describes a novel architecture for the hardware implementation of non-linear multi-layer cellular neural networks. This makes it feasible to design CNNs with millions o...
J. Javier Martínez-Álvarez, F. Javie...
FPGA
2009
ACM
343views FPGA» more  FPGA 2009»
14 years 2 months ago
Fpga-based face detection system using Haar classifiers
This paper presents a hardware architecture for face detection based system on AdaBoost algorithm using Haar features. We describe the hardware design techniques including image s...
Junguk Cho, Shahnam Mirzaei, Jason Oberg, Ryan Kas...
ICMCS
2005
IEEE
77views Multimedia» more  ICMCS 2005»
14 years 1 months ago
A quarter pel full search block motion estimation architecture for H.264/AVC
This paper presents a novel quarter pel full search block motion estimation architecture for H.264/AVC encoder. The proposed architecture is capable of calculating all 41 motion v...
Choudhury A. Rahman, Wael M. Badawy
SBCCI
2004
ACM
111views VLSI» more  SBCCI 2004»
14 years 25 days ago
A partial reconfigurable architecture for controllers based on Petri nets
Digital Control System in the industry has been used in most of the applications based on expensive Programmable Logical Controllers (PLC). These Systems are, in general, highly c...
Paulo Sérgio B. do Nascimento, Paulo Romero...
RTCSA
2005
IEEE
14 years 1 months ago
FPGA-Based Content Protection System for Embedded Consumer Electronics
We propose a new architecture for a content protection system that conceals confidential data and algorithms in an FPGA as electrical circuits. This architecture is designed for a...
Hiroyuki Yokoyama, Kenji Toda