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SAC
2006
ACM
14 years 1 months ago
Building the functional performance model of a processor
In this paper, we present an efficient procedure for building a piecewise linear function approximation of the speed function of a processor with hierarchical memory structure. Th...
Alexey L. Lastovetsky, Ravi Reddy, Robert Higgins
AAI
2008
101views more  AAI 2008»
13 years 7 months ago
A Replanning Algorithm for Decision Theoretic Hierarchical Planning: Principles and Empirical Evaluation
In this paper, we present a replanning algorithm for a decision-theoretic hierarchical planner, illustrate the experimental methodology we designed to investigate its performance,...
Guido Boella, Rossana Damiano
IPL
1998
80views more  IPL 1998»
13 years 7 months ago
The Economics of Large-Memory Computations
We propose, and justify, an economic theory to guide memory system design, operation, and analysis. Our theory treats memory random-access latency, and its cost per installed mega...
Clark D. Thomborson
IPPS
1998
IEEE
13 years 12 months ago
Performance Sensitivity of Space Sharing Processor Scheduling in Distributed-Memory Multicomputers
- Processor scheduling in distributed-memory systems has received considerable attention in recent years. Several commercial distributed-memory systems use spacesharing processor s...
Sivarama P. Dandamudi, Hai Yu
ICC
2007
IEEE
126views Communications» more  ICC 2007»
14 years 2 months ago
Evaluation of Grouping Strategies for an Hierarchical SDMA/TDMA Scheduling Process
Abstract— Adding SDMA capabilities to modern wireless communication systems like IEEE 802.16 WiMAX promises high system capacity gains but raises the problem of combining orthogo...
Christian Hoymann, Jan Ellenbeck, Ralf Pabst, Marc...