Sciweavers

875 search results - page 172 / 175
» A Factorial Performance Evaluation for Hierarchical Memory S...
Sort
View
LCTRTS
2007
Springer
14 years 1 months ago
Tetris: a new register pressure control technique for VLIW processors
The run-time performance of VLIW (very long instruction word) microprocessors depends heavily on the effectiveness of its associated optimizing compiler. Typical VLIW compiler pha...
Weifeng Xu, Russell Tessier
ICS
1998
Tsinghua U.
13 years 12 months ago
Data Prefetching for Software DSMs
In this paper we propose and evaluate the Adaptive++ technique, a novel runtime-only data prefetching strategy for software-based distributed shared-memory systems (software DSMs)...
Ricardo Bianchini, Raquel Pinto, Claudio Luis de A...
ADHOC
2007
135views more  ADHOC 2007»
13 years 7 months ago
Mitigating the gateway bottleneck via transparent cooperative caching in wireless mesh networks
Wireless mesh networks (WMNs) have been proposed to provide cheap, easily deployable and robust Internet access. The dominant Internet-access traffic from clients causes a congest...
Saumitra M. Das, Himabindu Pucha, Y. Charlie Hu
CGO
2007
IEEE
13 years 11 months ago
Shadow Profiling: Hiding Instrumentation Costs with Parallelism
In profiling, a tradeoff exists between information and overhead. For example, hardware-sampling profilers incur negligible overhead, but the information they collect is consequen...
Tipp Moseley, Alex Shye, Vijay Janapa Reddi, Dirk ...
HPCA
2008
IEEE
14 years 8 months ago
Automated microprocessor stressmark generation
Estimating the maximum power and thermal characteristics of a processor is essential for designing its power delivery system, packaging, cooling, and power/thermal management sche...
Ajay M. Joshi, Lieven Eeckhout, Lizy Kurian John, ...