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» A Fast FPGA Implementation of a General Purpose Neuron
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FPGA
2007
ACM
150views FPGA» more  FPGA 2007»
14 years 1 months ago
FPGA-friendly code compression for horizontal microcoded custom IPs
Shrinking time-to-market and high demand for productivity has driven traditional hardware designers to use design methodologies that start from high-level languages. However, meet...
Bita Gorjiara, Daniel Gajski
CLUSTER
2011
IEEE
12 years 7 months ago
Incorporating Network RAM and Flash into Fast Backing Store for Clusters
—We present Nswap2L, a fast backing storage system for general purpose clusters. Nswap2L implements a single device interface on top of multiple heterogeneous physical storage de...
Tia Newhall, Douglas Woos
ARC
2008
Springer
186views Hardware» more  ARC 2008»
13 years 9 months ago
FPGA-based Real-time Super-Resolution on an Adaptive Image Sensor
Recent technological advances in imaging industry have lead to the production of imaging systems with high density pixel sensors. However, their long exposure times limit their app...
Maria E. Angelopoulou, Christos-Savvas Bouganis, P...

Publication
266views
13 years 1 months ago
NeuFlow: A Runtime Reconfigurable Dataflow Processor for Vision
In this paper we present a scalable dataflow hard- ware architecture optimized for the computation of general- purpose vision algorithms—neuFlow—and a dataflow compiler—luaFl...
C. Farabet, B. Martini, B. Corda, P. Akselrod, E. ...
FPL
2009
Springer
100views Hardware» more  FPL 2009»
13 years 11 months ago
A virus scanning engine using a parallel finite-input memory machine and MPUs
This paper presents a virus scanning engine. After showing the difference between ClamAV (an anti-virus software) and SNORT (an intrusion detection software), we show a new archit...
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura,...