FPGA-friendly code compression for horizontal microcoded custom IPs

Shrinking time-to-market and high demand for productivity has driven traditional hardware designers to use design methodologies that start from high-level languages. However, meeting timing constraints of automatically generated IPs is often a challenging and time-consuming task that must be repeated every time the specification is modified. To address this issue, a new generation of IP-design technologies that is capable of generating custom datapaths as well as programming an existing one is developed. These technologies are often based on Horizontal Microcoded Architectures. Large code size is a well-know problem in HMAs, and is referred to as “code bloating” problem. In this paper, we study the code size of one of the new HMAbased technologies called NISC. We show that NISC code size can be several times larger than a typical RISC processor, and we propose several low-overhead dictionary-based code compression techniques to reduce the code size. Our compression algorithm lever...

• Type: Conference
• Year: 2007
• Where: FPGA
• Authors: Bita Gorjiara, Daniel Gajski
• Keywords: Code Compression Techniques, Code Size, FPGA 2007, Hardware, NISC Code Size