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» A Fault Modeling Technique to Test Memory BIST Algorithms
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DSD
2004
IEEE
97views Hardware» more  DSD 2004»
13 years 11 months ago
Scene Management Models and Overlap Tests for Tile-Based Rendering
Tile-based rendering (also called chunk rendering or bucket rendering) is a promising technique for low-power, 3D graphics platforms. This technique decomposes a scene into smalle...
Iosif Antochi, Ben H. H. Juurlink, Stamatis Vassil...
ISSTA
2009
ACM
14 years 2 months ago
Memory slicing
Traditional dynamic program slicing techniques are code-centric, meaning dependences are introduced between executed statement instances, which gives rise to various problems such...
Bin Xin, Xiangyu Zhang
IPPS
2009
IEEE
14 years 2 months ago
A fusion-based approach for tolerating faults in finite state machines
Given a set of n different deterministic finite state machines (DFSMs) modeling a distributed system, we examine the problem of tolerating f crash or Byzantine faults in such a ...
Vinit A. Ogale, Bharath Balasubramanian, Vijay K. ...
ICML
1997
IEEE
14 years 8 months ago
Predicting Multiprocessor Memory Access Patterns with Learning Models
Machine learning techniques are applicable to computer system optimization. We show that shared memory multiprocessors can successfully utilize machine learning algorithms for mem...
M. F. Sakr, Steven P. Levitan, Donald M. Chiarulli...
VLSID
2004
IEEE
139views VLSI» more  VLSID 2004»
14 years 8 months ago
Open Defects Detection within 6T SRAM Cells using a No Write Recovery Test Mode
The detection of all open defects within 6T SRAM cells is always a challenge due to the significant test time requirements. This paper proposes a new design-for-test (DFT) techniq...
André Ivanov, Baosheng Wang, Josh Yang