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» A Fault Tolerance Approach for Enterprise Applications
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DAC
2005
ACM
14 years 8 months ago
Fault and energy-aware communication mapping with guaranteed latency for applications implemented on NoC
As feature sizes shrink, transient failures of on-chip network links become a critical problem. At the same time, many applications require guarantees on both message arrival prob...
Sorin Manolache, Petru Eles, Zebo Peng
ICCD
2006
IEEE
94views Hardware» more  ICCD 2006»
14 years 4 months ago
Reliability Support for On-Chip Memories Using Networks-on-Chip
— As the geometries of the transistors reach the physical limits of operation, one of the main design challenges of Systems-on-Chips (SoCs) will be to provide dynamic (run-time) ...
Federico Angiolini, David Atienza, Srinivasan Mura...
WISES
2004
13 years 9 months ago
Embedded Real-Time-Tracer - An Approach with IDE
-- Debugging software that runs on highly integrated System-on-Chip devices is complicated because conventional debug tools (like traditional In-Circuit Emulators and Logic Analyze...
Babak Rahbaran, Matthias Függer, Andreas Stei...
PVM
2010
Springer
13 years 6 months ago
Dodging the Cost of Unavoidable Memory Copies in Message Logging Protocols
Abstract. With the number of computing elements spiraling to hundred of thousands in modern HPC systems, failures are common events. Few applications are nevertheless fault toleran...
George Bosilca, Aurelien Bouteiller, Thomas H&eacu...
IWSEC
2009
Springer
14 years 2 months ago
Tamper-Tolerant Software: Modeling and Implementation
Abstract. Common software-protection systems attempt to detect malicious observation and modification of protected applications. Upon tamper detection, anti-hacking code may produ...
Mariusz H. Jakubowski, Chit Wei Saw, Ramarathnam V...