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SI3D
1997
ACM
13 years 12 months ago
Post-rendering 3D warping
A pair of rendered images and their Z-buffers contain almost all of the information necessary to re-render from nearby viewpoints. For the small changes in viewpoint that occur in...
William R. Mark, Leonard McMillan, Gary Bishop
FCCM
2004
IEEE
152views VLSI» more  FCCM 2004»
13 years 11 months ago
Implementing and Evaluating Stream Applications on the Dynamically Reconfigurable Processor
Dynamically Reconfigurable Processor (DRP)[1] developed by NEC Electronics is a coarse grain reconfigurable processor that selects a data path from the on-chip repository of sixte...
Noriaki Suzuki, Shunsuke Kurotaki, Masayasu Suzuki...
OSDI
1994
ACM
13 years 9 months ago
Performance Issues in Parallelized Network Protocols
Parallel processing has been proposed as a means of improving network protocol throughput. Several different strategies have been taken towards parallelizing protocols. A relative...
Erich M. Nahum, David J. Yates, James F. Kurose, D...
ICIAP
1999
ACM
14 years 2 days ago
Random Walk Approach to Image Enhancement
The paper presents a new technique of image enhancement. The described algorithm enables the suppression of noise and contrast enhancement. The interesting feature of this new alg...
Bogdan Smolka, Konrad W. Wojciechowski, Marek Szcz...
ISPD
2003
ACM
110views Hardware» more  ISPD 2003»
14 years 1 months ago
Explicit gate delay model for timing evaluation
Delay evaluation is always a crucial concern in the VLSI design and it becomes increasingly more critical in the nowadays deep-submicron technology. To obtain an accurate delay va...
Muzhou Shao, Martin D. F. Wong, Huijing Cao, Youxi...