Explicit gate delay model for timing evaluation

Delay evaluation is always a crucial concern in the VLSI design and it becomes increasingly more critical in the nowadays deep-submicron technology. To obtain an accurate delay value, the gate modeling is a key issue. As the VLSI feature size scaling down and meanwhile operating frequency increasing, the modeling work becomes more difficult than ever for high-performance digital ICs. Nevertheless, most conventional techniques of gate modeling are based on the switch-resistor model (i.e., a voltage source concatenating a driving resistance), which can only capture the gate characteristic in its switching region. Hence, these modeling techniques have to decouple the gate with its interconnects and compute a piecewise linear function for the driving source in the iterative computation of effective capacitance [1, 3, 4]. Since the driving source of the model is dependent on gate load, when the design modification affects the load, the gate has to be modeled again almost from the beginn...

• Type: Conference
• Year: 2003
• Where: ISPD
• Authors: Muzhou Shao, Martin D. F. Wong, Huijing Cao, Youxin Gao, Li-Pen Yuan, Li-Da Huang, Seokjin Lee
• Keywords: Gate, Gate Load, Gate Modeling, Hardware, ISPD 2003