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» A Field-Programmable Mixed-Analog-Digital Array
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CSREAESA
2010
13 years 7 months ago
The First Clock Cycle Is A Real BIST
The primary goal of Built-In Self-Test (BIST) for Field Programmable Gate Arrays (FPGAs) is to completely test all programmable logic and routing resources in the device such that ...
Charles E. Stroud, Bradley F. Dutton
FPL
2010
Springer
170views Hardware» more  FPL 2010»
13 years 7 months ago
IP Based Configurable SIMD Massively Parallel SoC
Significant advances in the field of configurable computing have enabled parallel processing within a single FieldProgrammable Gate Array (FPGA) chip. This paper presents the imple...
Mouna Baklouti, Mohamed Abid, Philippe Marquet, Je...
FPL
2010
Springer
139views Hardware» more  FPL 2010»
13 years 7 months ago
Mapping Multiple Multivariate Gaussian Random Number Generators on an FPGA
A Multivariate Gaussian random number generator (MVGRNG) is an essential block for many hardware designs, including Monte Carlo simulations. These simulations are usually used in a...
Chalermpol Saiprasert, Christos-Savvas Bouganis, G...
IJNSEC
2010
247views more  IJNSEC 2010»
13 years 4 months ago
Hardware Implementation of Efficient Modified Karatsuba Multiplier Used in Elliptic Curves
The efficiency of the core Galois field arithmetic improves the performance of elliptic curve based public key cryptosystem implementation. This paper describes the design and imp...
Sameh M. Shohdy, Ashraf El-Sisi, Nabil A. Ismail
TC
2010
13 years 4 months ago
Performance Comparison of Graphics Processors to Reconfigurable Logic: A Case Study
A systematic approach to the comparison of the graphics processor (GPU) and reconfigurable logic is defined in terms of three throughput drivers. The approach is applied to five ca...
Ben Cope, Peter Y. K. Cheung, Wayne Luk, Lee W. Ho...