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» A Field-Programmable Mixed-Analog-Digital Array
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IPPS
2007
IEEE
14 years 5 months ago
Miss Ratio Improvement For Real-Time Applications Using Fragmentation-Aware Placement
Partially reconfigurable Field-Programmable Gate Arrays (FPGAs) allow parts of the chip to be configured at run-time where each part could hold an independent task. Online place...
Ahmed Abou ElFarag, Hatem M. El-Boghdadi, Samir I....
FPGA
2007
ACM
185views FPGA» more  FPGA 2007»
14 years 5 months ago
Power-aware FPGA logic synthesis using binary decision diagrams
Power consumption in field programmable gate arrays (FPGAs) has become an important issue as the FPGA market has grown to include mobile platforms. In this work we present a power...
Kevin Oo Tinmaung, David Howland, Russell Tessier
ISVC
2007
Springer
14 years 5 months ago
Motion Projection for Floating Object Detection
Abstract. Floating mines are a significant threat to the safety of ships in theatres of military or terrorist conflict. Automating mine detection is difficult, due to the unpredict...
Zhaoyi Wei, Dah-Jye Lee, David Jilk, Robert B. Sch...
ICPADS
2006
IEEE
14 years 5 months ago
Scalable Hybrid Designs for Linear Algebra on Reconfigurable Computing Systems
—Recently, high-end reconfigurable computing systems that employ Field-Programmable Gate Arrays (FPGAs) as hardware accelerators for general-purpose processors have been built. T...
Ling Zhuo, Viktor K. Prasanna
IPPS
2006
IEEE
14 years 5 months ago
An optimal architecture for a DDC
Digital Down Conversion (DDC) is an algorithm, used to lower the amount of samples per second by selecting a limited frequency band out of a stream of samples. A possible DDC algo...
Tjerk Bijlsma, Pascal T. Wolkotte, Gerard J. M. Sm...