Power-aware FPGA logic synthesis using binary decision diagrams

Power consumption in field programmable gate arrays (FPGAs) has become an important issue as the FPGA market has grown to include mobile platforms. In this work we present a power-aware logic optimization tool that is specialized to facilitate subsequent power-aware technology mapping. Our synthesis framework uses binary decision diagram (BDD) based collapsing and decomposition techniques in conjunction with signal switching estimates to achieve power-efficient circuit networks. The results of synthesis and subsequent power-aware technology mapping are evaluated using two distinct physical design platforms: academic VPR and Altera Quartus II. Our approach achieves an average energy reduction of 13% for Altera Cyclone II devices versus synthesis with SIS-based algebraic optimization at the cost of 11% average circuit performance if performance-optimal technology mapping is performed after synthesis. If technology mapping is tuned to achieve the same average delay for both SIS and BDD-b...

• Type: Conference
• Year: 2007
• Where: FPGA
• Authors: Kevin Oo Tinmaung, David Howland, Russell Tessier
• Keywords: FPGA 2007, Hardware, Power-aware Technology Mapping, Subsequent Power-aware Technology, Technology Mapping