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    ERSA
    2006
    99views Hardware» more  ERSA 2006»
    Low Power Programmable FIR Filtering IP Cores Targeting System-on-a-Reprogrammable-Chip (SoRC)
    13 years 8 months ago
    Low Power Programmable FIR Filtering IP Cores Targeting System-on-a-Reprogrammable-Chip (SoRC)
    Download  ww1.ucmss.com
    - This paper presents the design and implementation methodology of some low power programmable FIR filtering IP cores targeting SoRC and compares their performance in term of area,...
    Muhammad Akhtar Khan, Abdul Hameed, Ahmet T. Erdog...
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    AAAI
    1998
    120views Intelligent Agents» more  AAAI 1998»
    Evolvable Hardware Chip for High Precision Printer Image Compression
    13 years 8 months ago
    Evolvable Hardware Chip for High Precision Printer Image Compression
    Download  www.aaai.org
    This paper describes a data compression chip for the high-precision electrophotographic printer using Evolvable Hardware (EHW). EHW is a new hardware paradigm which combines Genet...
    Hidenori Sakanashi, Mehrdad Salami, Masaya Iwata, ...
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    WCE
    2007
    112views Electrical And Computer Engi...» more  WCE 2007»
    High-Performance Multigrid Solvers in Reconfigurable Hardware
    13 years 8 months ago
    High-Performance Multigrid Solvers in Reconfigurable Hardware
    Download  www.iaeng.org
    —Partial Differential Equations (PDEs) play an essential role in modeling real world problems. The broad field of modeling such systems has drawn the researchers’ attention for...
    Safaa J. Kasbah, Issam W. Damaj
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    CSREAESA
    2009
    175views Embedded Systems» more  CSREAESA 2009»
    Built-In Self-Test of Embedded SEU Detection Cores in Virtex-4 and Virtex-5 FPGAs
    13 years 8 months ago
    Built-In Self-Test of Embedded SEU Detection Cores in Virtex-4 and Virtex-5 FPGAs
    Download  www.eng.auburn.edu
    A Built-In Self-Test (BIST) approach is presented for the Internal Configuration Access Port (ICAP) and Frame Error Correcting Code (ECC) logic cores embedded in Xilinx Virtex-4 an...
    Bradley F. Dutton, Charles E. Stroud
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    CSREAESA
    2009
    180views Embedded Systems» more  CSREAESA 2009»
    Embedded Processor Based Fault Injection and SEU Emulation for FPGAs
    13 years 8 months ago
    Embedded Processor Based Fault Injection and SEU Emulation for FPGAs
    Download  www.eng.auburn.edu
    Two embedded processor based fault injection case studies are presented which are applicable to Field Programmable Gate Arrays (FPGAs) and FPGA cores in configurable System-on-Chip...
    Bradley F. Dutton, Mustafa Ali, Charles E. Stroud,...
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