107 search results - page 4 / 22 » A Fine-Grain Parallel Architecture Based on Barrier Synchron... |
HPCA
2004
IEEE
14 years 7 months ago
2004
IEEE
Much research has been devoted to making microprocessors energy-efficient. However, little attention has been paid to multiprocessor environments where, due to the co-operative na...
CASES
2008
ACM
13 years 8 months ago
2008
ACM
Interconnects based on Networks-on-Chip are an appealing solution to address future microprocessor designs where, very likely, hundreds of cores will be connected on a single chip...
ISCA
1995
IEEE
13 years 10 months ago
1995
IEEE
Latency tolerance is essential in achieving high performance on parallel computers for remote function calls and fine-grained remote memory accesses. EM-X supports interprocessor ...
CONEXT
2010
ACM
13 years 4 months ago
2010
ACM
TCP incast congestion happens in high-bandwidth and lowlatency networks, when multiple synchronized servers send data to a same receiver in parallel [15]. For many important data ...
DAC
2002
ACM
14 years 7 months ago
2002
ACM
Aim of this paper is to propose a methodology for the definition of an instruction-level energy estimation framework for VLIW (Very Long Instruction Word) processors. The power mo...