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» A Formal Specification of dMARS
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EURODAC
1994
IEEE
127views VHDL» more  EURODAC 1994»
14 years 1 months ago
A process algebra interpretation of a verification oriented overlanguage of VHDL
The VOVHDL language was defined as a verification oriented VHDL
Catherine Bayol, Bernard Soulas, Dominique Borrion...
ENTCS
2006
130views more  ENTCS 2006»
13 years 9 months ago
LSC Verification for UML Models with Unbounded Creation and Destruction
The approaches to automatic formal verification of UML models known up to now require a finite bound on the number of objects existing at each point in time. In [4] we have observ...
Bernd Westphal
JUCS
2002
146views more  JUCS 2002»
13 years 8 months ago
A Framework for Semantics of UML Sequence Diagrams in PVS
: This paper presents a framework for representing formal semantics of a subset of the Unified Modeling Language (UML) notation in a higher-order logic, more specifically semantics...
Demissie B. Aredo
UML
1998
Springer
14 years 1 months ago
Supporting Disciplined Reuse and Evolution of UML Models
UML provides very little support for modelling evolvable or reusable specifications and designs. To cope with this problem, the UML needs to be extended with support for reuse and ...
Tom Mens, Carine Lucas, Patrick Steyaert
LPAR
2000
Springer
14 years 21 days ago
Encoding Temporal Logics in Executable Z: A Case Study for the ZETA System
Abstract. The ZETA system is a Z-based tool environment for developing formal specifications. It contains a component for executing the Z language based on the implementation techn...
Wolfgang Grieskamp, Markus Lepper