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» A Formal Specification of dMARS
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CODES
2007
IEEE
14 years 1 months ago
Synchronization after design refinements with sensitive delay elements
The synchronous computational model with its simple computation and communication mechanism makes it easy to describe, simulate and formally verify synchronous embedded systems at...
Tarvo Raudvere, Ingo Sander, Axel Jantsch
DAC
2007
ACM
14 years 1 months ago
Memory Modeling in ESL-RTL Equivalence Checking
When designers create RTL models from a system-level specification, arrays in the system-level model are often implemented as memories in the RTL. Knowing the correspondence betwe...
Alfred Kölbl, Jerry R. Burch, Carl Pixley
WEBDB
2010
Springer
238views Database» more  WEBDB 2010»
14 years 1 months ago
An Agglomerative Query Model for Discovery in Linked Data: Semantics and Approach
Data on the Web is increasingly being used for discovery and exploratory tasks. Unlike traditional fact-finding tasks that require only the typical single-query and response parad...
Sidan Gao, Haizhou Fu, Kemafor Anyanwu
EDBT
2009
ACM
128views Database» more  EDBT 2009»
14 years 1 months ago
HIDE: heterogeneous information DE-identification
While there is an increasing need to share data that may contain personal information, such data sharing must preserve individual privacy without disclosing any identifiable infor...
James J. Gardner, Li Xiong, Kanwei Li, James J. Lu
ACSD
2004
IEEE
118views Hardware» more  ACSD 2004»
14 years 1 months ago
Verification and Implementation of Delay-Insensitive Processes in Restrictive Environments
Abstract. A delay-insensitive module communicates with its environment through wires of unbounded delay. To avoid transmission interference, the absorption of a signal transition m...
Hemangee K. Kapoor, Mark B. Josephs, Dennis P. Fur...