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» A Functional DBPL Revealing High Level Optimizations
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VLSI
2005
Springer
14 years 2 months ago
Technology Mapping for Area Optimized Quasi Delay Insensitive Circuits
Quasi delay insensitive circuits are functionally independent of delays in gates and wires (except for some particular wires). Such asynchronous circuits offer high robustness but...
Bertrand Folco, Vivian Brégier, Laurent Fes...
BMCBI
2005
178views more  BMCBI 2005»
13 years 8 months ago
A quantization method based on threshold optimization for microarray short time series
Background: Reconstructing regulatory networks from gene expression profiles is a challenging problem of functional genomics. In microarray studies the number of samples is often ...
Barbara Di Camillo, Fatima Sanchez-Cabo, Gianna To...
CORR
2010
Springer
138views Education» more  CORR 2010»
13 years 8 months ago
Optimal Path Planning under Temporal Logic Constraints
Abstract-- In this paper we present a method for automatically generating optimal robot trajectories satisfying high level mission specifications. The motion of the robot in the en...
Stephen L. Smith, Jana Tumova, Calin Belta, Daniel...
JSS
2002
90views more  JSS 2002»
13 years 8 months ago
Producing reliable software: an experiment
A customer of high assurance software recently sponsored a software engineering experiment in which a small real-time software system was developed concurrently by two popular sof...
Carol Smidts, Xin Huang, James C. Widmaier
IRI
2007
IEEE
14 years 3 months ago
Reuse Technique in Hardware Design
The paper presents a technique for the design of digital systems on the basis of reusable hardware templates, which are circuits with modifiable functionality that might be custom...
Valery Sklyarov, Iouliia Skliarova