Network on Chip (NoC) is a new paradigm for designing core based System on Chips. It supports high degree of reusability and is scalable. In this paper, an efficient Two-Step Gene...
A genetic algorithm approach for segmented channel routing in field programmable gate arrays (FPGA's) is presented in this paper. The FPGA segmented channel routing problem (F...
This work addresses the problem of finding the adjustable parameters of a learning algorithm using Genetic Algorithms. This problem is also known as the model selection problem. In...
This paper describes a methodology for designing interconnected LAN-MAN networks with the objective of minimizing the average network delay. We consider IEEE 802.3-5 LANs intercon...
This paper deals with the generation of balanced incomplete block designs (BIBD), a hard constrained combinatorial problem with multiple applications. This problem is here formulat...