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ICCAD
2006
IEEE
131views Hardware» more  ICCAD 2006»
14 years 4 months ago
High-level synthesis challenges and solutions for a dynamically reconfigurable processor
A dynamically reconfigurable processor (DRP) is designed to achieve high area efficiency by switching reconfigurable data paths dynamically. Our DRP architecture has a stand alone...
Takao Toi, Noritsugu Nakamura, Yoshinosuke Kato, T...
SAC
2010
ACM
13 years 2 months ago
Convex onion peeling genetic algorithm: an efficient solution to map labeling of point-feature
Map labeling of point-feature is the problem of placing text labels to corresponding point features on a map in a way that minimizes overlaps while satisfying basic rules for the ...
Wan D. Bae, Shayma Alkobaisi, Petr Vojtechovsk&yac...
KDD
1995
ACM
112views Data Mining» more  KDD 1995»
13 years 11 months ago
Learning First Order Logic Rules with a Genetic Algorithm
This paper introduces a newalgorithm called SIAO1 for learning first order logic rules withgenetic algorithms. SIAO1uses the covering principle developed in AQwhereseed examplesar...
Sébastien Augier, Gilles Venturini, Yves Ko...
BMCBI
2006
239views more  BMCBI 2006»
13 years 7 months ago
Applying dynamic Bayesian networks to perturbed gene expression data
Background: A central goal of molecular biology is to understand the regulatory mechanisms of gene transcription and protein synthesis. Because of their solid basis in statistics,...
Norbert Dojer, Anna Gambin, Andrzej Mizera, Bartek...
ICCAD
2008
IEEE
140views Hardware» more  ICCAD 2008»
14 years 4 months ago
Algorithms for simultaneous consideration of multiple physical synthesis transforms for timing closure
We propose a post-placement physical synthesis algorithm that can apply multiple circuit synthesis and placement transforms on a placed circuit to improve the critical path delay ...
Huan Ren, Shantanu Dutt