ICCAD 2008 - PDF Preprint Papers

ICCAD 2008 International Conference on Computer-Aided Design

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ICCAD
2008
IEEE

246views Hardware» more ICCAD 2008»

MC-Sim: an efficient simulation tool for MPSoC designs

14 years 8 months ago

Download cadlab.cs.ucla.edu

The ability to integrate diverse components such as processor cores, memories, custom hardware blocks and complex network-on-chip (NoC) communication frameworks onto a single chip...

Jason Cong, Karthik Gururaj, Guoling Han, Adam Kap...

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Id	Views	Title	Status

1	246	MC-Sim: an efficient simulation tool for MPSoC designs	claim
2	246	Integrated circuit design with NEM relays	claim
3	223	Decoupling capacitance allocation for timing with statistical noise model and timing analysis	claim
4	200	Accurate Equivalent Energy Breakeven Time Estimation for Power Gating
5	177	Double patterning technology friendly detailed routing	claim
6	172	Frequency-aware PPV: a robust phase macromodel for accurate oscillator noise analysis	claim
7	170	Obstacle-avoiding rectilinear Steiner tree construction	claim
8	170	A polynomial time approximation scheme for timing constrained minimum cost layer assignment	claim
9	162	MAPS: multi-algorithm parallel circuit simulation	claim
10	161	A low-overhead fault tolerance scheme for TSV-based 3D network on chip links	claim
11	153	Breaking the simulation barrier: SRAM evaluation through norm minimization	claim
12	153	Boolean factoring and decomposition of logic networks	claim
13	153	SPM management using Markov chain based data access prediction	claim
14	151	Race analysis for SystemC using model checking	claim
15	150	Performance estimation and slack matching for pipelined asynchronous architectures with choice	claim
16	147	Overlay aware interconnect and timing variation modeling for double patterning technology	claim
17	141	Layout decomposition for double patterning lithography	claim
18	140	Correct-by-construction microarchitectural pipelining	claim
19	140	Algorithms for simultaneous consideration of multiple physical synthesis transforms for timing closure	claim
20	140	To SAT or not to SAT: Ashenhurst decomposition in a large scale	claim
21	138	Fault tolerant placement and defect reconfiguration for nano-FPGAs	claim
22	133	Module locking in biochemical synthesis	claim
23	130	Lightweight secure PUFs	claim
24	130	Area-I/O flip-chip routing for chip-package co-design	claim
25	129	A capacitance solver for incremental variation-aware extraction	claim
26	129	Path-RO: a novel on-chip critical path delay measurement under process variations	claim
27	127	Verification of arithmetic datapaths using polynomial function models and congruence solving	claim
28	127	System-level power estimation using an on-chip bus performance monitoring unit	claim
29	127	Design and optimization of a digital microfluidic biochip for protein crystallization	claim
30	127	Efficient and accurate eye diagram prediction for high speed signaling	claim
31	125	A succinct memory model for automated design debugging	claim
32	125	Practical, fast Monte Carlo statistical static timing analysis: why and how	claim
33	122	Network flow-based power optimization under timing constraints in MSV-driven floorplanning	claim
34	117	On the numbers of variables to represent sparse logic functions	claim
35	117	A novel sequential circuit optimization with clock gating logic	claim
36	116	Optimization-based framework for simultaneous circuit-and-system design-space exploration: a high-speed link example	claim
37	115	Minimizing the energy cost of throughput in a linear pipeline by opportunistic time borrowing	claim
38	110	NTHU-Route 2.0: a fast and stable global router	claim
39	110	Comprehensive procedure for fast and accurate coupled oscillator network simulation	claim
40	109	Verifying external interrupts of embedded microprocessor in SoC with on-chip bus	claim
41	109	Transition-aware decoupling-capacitor allocation in power noise reduction	claim
42	108	FBT: filled buffer technique to reduce code size for VLIW processors	claim
43	108	Multi-layer global routing considering via and wire capacities	claim
44	107	Importance sampled circuit learning ensembles for robust analog IC design	claim
45	107	Constrained aggressor set selection for maximum coupling noise	claim
46	106	Process variability-aware transient fault modeling and analysis	claim
47	105	Parameterized transient thermal behavioral modeling for chip multiprocessors	claim
48	105	Temperature-aware test scheduling for multiprocessor systems-on-chip	claim
49	103	Graphene nanoribbon FETs: technology exploration and CAD	claim
50	103	On capture power-aware test data compression for scan-based testing	claim
51	103	Pyramids: an efficient computational geometry-based approach for timing-driven placement	claim
52	103	Hardware protection and authentication through netlist level obfuscation	claim
53	99	Evaluation of voltage interpolation to address process variations	claim
54	98	Statistical path selection for at-speed test	claim
55	98	Performance optimization of elastic systems using buffer resizing and buffer insertion	claim
56	98	Scalable and scalably-verifiable sequential synthesis	claim
57	97	Integrated code and data placement in two-dimensional mesh based chip multiprocessors	claim
58	97	Guiding global placement with wire density	claim
59	96	Post-silicon timing characterization by compressed sensing	claim
60	93	Linear constraint graph for floorplan optimization with soft blocks	claim
61	89	Temperature aware task sequencing and voltage scaling	claim
62	87	Routing for chip-package-board co-design considering differential pairs	claim
63	86	Robust FPGA resynthesis based on fault-tolerant Boolean matching	claim
64	85	Guaranteed stable projection-based model reduction for indefinite and unstable linear systems	claim
65	84	A voltage-frequency island aware energy optimization framework for networks-on-chip	claim
66	83	Linear analysis of random process variability	claim
67	80	Advancing supercomputer performance through interconnection topology synthesis	claim

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