Sciweavers

74 search results - page 10 / 15
» A Hardware Acceleration Unit for MPI Queue Processing
Sort
View
JCC
2010
105views more  JCC 2010»
13 years 5 months ago
PAPER - Accelerating parallel evaluations of ROCS
Abstract: Modern graphics processing units (GPUs) are flexibly programmable and have peak computational throughput significantly faster than conventional CPUs. Herein, we describ...
Imran S. Haque, Vijay S. Pande
ISPASS
2010
IEEE
14 years 2 months ago
Visualizing complex dynamics in many-core accelerator architectures
—While many-core accelerator architectures, such as today’s Graphics Processing Units (GPUs), offer orders of magnitude more raw computing power than contemporary CPUs, their m...
Aaron Ariel, Wilson W. L. Fung, Andrew E. Turner, ...
ERSA
2007
194views Hardware» more  ERSA 2007»
13 years 8 months ago
A Scalable and Reconfigurable Shared-Memory Graphics Cluster Architecture
Abstract: If the computational demands of an interactive graphics rendering application cannot be met by a single commodity Graphics Processing Unit (GPU), multiple graphics accele...
Ross Brennan, Michael Manzke, Keith O'Conor, John ...
MICRO
2009
IEEE
147views Hardware» more  MICRO 2009»
14 years 2 months ago
Complexity effective memory access scheduling for many-core accelerator architectures
Modern DRAM systems rely on memory controllers that employ out-of-order scheduling to maximize row access locality and bank-level parallelism, which in turn maximizes DRAM bandwid...
George L. Yuan, Ali Bakhoda, Tor M. Aamodt
RSP
2008
IEEE
120views Control Systems» more  RSP 2008»
14 years 1 months ago
Co-design Architecture and Implementation for Point-Based Rendering on FPGAs
Current graphic cards include advanced graphic processing units to accelerate the rendering of 3D objects with millions of polygons. As object models grow in complexity, the rende...
Mateusz Majer, Stefan Wildermann, Josef Angermeier...