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» A Hardware Algorithm for Integer Division
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DSD
2004
IEEE
106views Hardware» more  DSD 2004»
14 years 11 days ago
Finite Precision Analysis of Support Vector Machine Classification in Logarithmic Number Systems
In this paper we present an analysis of the minimal hardware precision required to implement Support Vector Machine (SVM) classification within a Logarithmic Number System archite...
Faisal M. Khan, Mark G. Arnold, William M. Potteng...
CHES
2003
Springer
119views Cryptology» more  CHES 2003»
14 years 1 months ago
Faster Double-Size Modular Multiplication from Euclidean Multipliers
Abstract. A novel technique for computing a 2n-bit modular multiplication using n-bit arithmetic was introduced at CHES 2002 by Fischer and Seifert. Their technique makes use of an...
Benoît Chevallier-Mames, Marc Joye, Pascal P...
GLVLSI
2007
IEEE
158views VLSI» more  GLVLSI 2007»
14 years 3 months ago
Design of a versatile and cost-effective hybrid floating-point/LNS arithmetic processor
LNS (logarithmic number system) arithmetic has the advantages of high-precision and high performance in complex function computation. However, the large hardware problem in LNS ad...
Chichyang Chen, Paul Chow
WSC
1998
13 years 10 months ago
Evaluating Adaptive Signal Control Using CORSIM
This paper discusses the evaluation of adaptive traffic signal control using TSIS/CORSIM. The paper reviews three adaptive control strategies that have been developed through cont...
Charles Stallard, Larry E. Owen
MOBIHOC
2009
ACM
14 years 9 months ago
Demonstration of highly programmable downlink OFDMA (WiMax) transceivers for SDR systems
In this paper, we present the architecture of a highly configurable multi-input multi?output (MIMO) orthogonal frequency division multiple access (OFDMA) platform. The platform is...
Hamid Eslami, Gaurav Patel, Chitaranjan P. Sukumar...