Sciweavers

1998 search results - page 137 / 400
» A Hardware Implementation of PRAM and Its Performance Evalua...
Sort
View
APCSAC
2006
IEEE
14 years 3 months ago
A High Performance Simulator System for a Multiprocessor System Based on a Multi-way Cluster
In the ubiquitous era, it is necessary to research the architectures of multiprocessor system with high performance and low power consumption. A simulator developed in high level l...
Arata Shinozaki, Masatoshi Shima, Minyi Guo, Mitsu...
VEE
2009
ACM
157views Virtualization» more  VEE 2009»
14 years 4 months ago
Task-aware virtual machine scheduling for I/O performance
The use of virtualization is progressively accommodating diverse and unpredictable workloads as being adopted in virtual desktop and cloud computing environments. Since a virtual ...
Hwanju Kim, Hyeontaek Lim, Jinkyu Jeong, Heeseung ...
ICDCS
2007
IEEE
14 years 3 months ago
STEP: Sequentiality and Thrashing Detection Based Prefetching to Improve Performance of Networked Storage Servers
State-of-the-art networked storage servers are equipped with increasingly powerful computing capability and large DRAM memory as storage caches. However, their contribution to the...
Shuang Liang, Song Jiang, Xiaodong Zhang
TVLSI
2008
164views more  TVLSI 2008»
13 years 9 months ago
Dynamically Configurable Bus Topologies for High-Performance On-Chip Communication
The on-chip communication architecture is a major determinant of overall performance in complex System-on-Chip (SoC) designs. Since the communication requirements of SoC components...
Krishna Sekar, Kanishka Lahiri, Anand Raghunathan,...
NOCS
2007
IEEE
14 years 3 months ago
On Characterizing Performance of the Cell Broadband Engine Element Interconnect Bus
Abstract – With the rise of multicore computing, the design of onchip networks (or networks on chip) has become an increasingly important component of computer architecture. The ...
Thomas William Ainsworth, Timothy Mark Pinkston