1998 search results - page 71 / 400 » A Hardware Implementation of PRAM and Its Performance Evalua... |
ICS
2004
Tsinghua U.
14 years 2 months ago
2004
Tsinghua U.
The Cray X1 was recently introduced as the first in a new line of parallel systems to combine high-bandwidth vector processing with an MPP system architecture. Alongside capabili...
MSS
2007
IEEE
14 years 3 months ago
2007
IEEE
Storage systems are increasingly subject to attacks. Cryptographic file systems mitigate the danger of exposing data by using encryption and integrity protection methods and guar...
CDC
2009
IEEE
14 years 1 months ago
2009
IEEE
Abstract-- Dataflow representations of Digital Signal Processing (DSP) software have been developing since the 1980's. They have proven to be useful in identifying bottlenecks...
ICCAD
2007
IEEE
14 years 6 months ago
2007
IEEE
— Small gates, such as AND2, XOR2 and MUX2, have been mixed with lookup tables (LUTs) inside the programmable logic block (PLB) to reduce area and power and increase performance ...
GLVLSI
2005
IEEE
14 years 2 months ago
2005
IEEE
In this paper we propose an FPGA implementation of a multi protocol Weighted Fair (WF) queuing algorithm able to handle variable length packets targeted for Packet Over Sonet (POS...