Design, synthesis and evaluation of heterogeneous FPGA with mixed LUTs and macro-gates

— Small gates, such as AND2, XOR2 and MUX2, have been mixed with lookup tables (LUTs) inside the programmable logic block (PLB) to reduce area and power and increase performance in FPGAs. However, it is unclear whether incorporating macro-gates with wide inputs inside PLBs is beneficial. In this paper, we first propose a methodology to extract a small set of logic functions that are able to implement a large portion of functions for given FPGA applications. Assuming that the extracted logic functions are implemented by macro-gates in PLBs, we then develop a complete synthesis flow for such heterogeneous PLBs with mixed LUTs and macro-gates. The flow includes a cut-based delay and area optimized technology mapping, a mixed binary integer and linear programming based area recovery algorithm to balance the resource utilization of macro-gates and LUTs for area-efficient packing, and a SATbased packing. We finally evaluate the proposed heterogeneous FPGA using the newly developed �...

• Type: Conference
• Year: 2007
• Where: ICCAD
• Authors: Yu Hu, Satyaki Das, Steven Trimberger, Lei He
• Keywords: Extracted Logic Functions, Hardware, ICCAD 2007, Mixed Binary Integer, Programmable Logic Block