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FPL
2001
Springer
87views Hardware» more  FPL 2001»
14 years 1 months ago
Parameterized Function Evaluation for FPGAs
This paper presents parameterized module-generators for pipelined function evaluation using lookup tables, adders, shifters and multipliers. We discuss trade-offs involved between...
Oskar Mencer, Nicolas Boullis, Wayne Luk, Henry St...
ISVLSI
2007
IEEE
100views VLSI» more  ISVLSI 2007»
14 years 3 months ago
Vector Processing Support for FPGA-Oriented High Performance Applications
In this paper, we propose and implement a vector processing system that includes two identical vector microprocessors embedded in two FPGA chips. Each vector microprocessor suppor...
Hongyan Yang, Shuai Wang, Sotirios G. Ziavras, Jie...
APPT
2009
Springer
14 years 3 months ago
Computational Performance of a Parallelized Three-Dimensional High-Order Spectral Element Toolbox
In this paper, a comprehensive performance review of an MPI-based high-order three-dimensional spectral element method C++ toolbox is presented. The focus is put on the performance...
Christoph Bosshard, Roland Bouffanais, Christian C...
IPPS
1994
IEEE
14 years 1 months ago
Parallel Evaluation of a Parallel Architecture by Means of Calibrated Emulation
A parallel transputer-based emulator has been developed to evaluate the DDM--ahighlyparallel virtual shared memory architecture. The emulator provides performance results of a har...
Henk L. Muller, Paul W. A. Stallard, David H. D. W...
ASPDAC
2006
ACM
148views Hardware» more  ASPDAC 2006»
14 years 3 months ago
An automated design flow for 3D microarchitecture evaluation
- Although the emerging three-dimensional integration technology can significantly reduce interconnect delay, chip area, and power dissipation in nanometer technologies, its impact...
Jason Cong, Ashok Jagannathan, Yuchun Ma, Glenn Re...