Parameterized Function Evaluation for FPGAs

This paper presents parameterized module-generators for pipelined function evaluation using lookup tables, adders, shifters and multipliers. We discuss trade-offs involved between (1) full-lookup tables, (2) bipartite (lookup-add) units, (3) lookup-multiply units, and (4) shift-and-add based CORDIC units. For lookup-multiply units we provide equations estimating approximation errors and rounding errors which are used to parameterize the hardware units. The resources and performance of the resulting design can be estimated given the input parameters. The method is implemented as part of the PAMBlox module generation environment. An example shows that the table-multiply unit produces competitive designs with data widths up to 20 bits when compared with shiftand-add based CORDIC units. Additionally, the table-multiply method can be used for larger data widths when evaluating functions not supported by CORDIC.

• Type: Conference
• Year: 2001
• Where: FPL
• Authors: Oskar Mencer, Nicolas Boullis, Wayne Luk, Henry Styles
• Keywords: CORDIC Units, Data Widths, FPL 2001, Hardware, Lookup-multiply Units