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» A Heterogeneous Lightweight Multithreaded Architecture
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ANCS
2007
ACM
14 years 1 months ago
Ruler: high-speed packet matching and rewriting on NPUs
Programming specialized network processors (NPU) is inherently difficult. Unlike mainstream processors where architectural features such as out-of-order execution and caches hide ...
Tomas Hruby, Kees van Reeuwijk, Herbert Bos
CCGRID
2005
IEEE
14 years 3 months ago
OGSA-based grid workload monitoring
In heterogeneous and dynamic distributed systems like the Grid, detailed monitoring of workload and its resulting system performance (e.g. response time) is required to facilitate...
Rui Zhang, Steve Moyle, Steve McKeever, Stephen He...
CASES
2007
ACM
14 years 1 months ago
An integrated ARM and multi-core DSP simulator
In this paper we describe the design and implementation of a flexible, and extensible, just-in-time ARM simulator designed to run co-operatively with a multi-core DSP simulator on...
Sharad Singhai, MingYung Ko, Sanjay Jinturkar, May...
MICRO
2010
IEEE
111views Hardware» more  MICRO 2010»
13 years 4 months ago
Putting Faulty Cores to Work
Since the non-cache parts of a core are less regular, compared to on-chip caches, tolerating manufacturing defects in the processing core is a more challenging problem. Due to the ...
Amin Ansari, Shuguang Feng, Shantanu Gupta, Scott ...
DSN
2003
IEEE
14 years 3 months ago
Integrating Recovery Strategies into a Primary Substation Automation System
The DepAuDE architecture provides middleware to integrate fault tolerance support into distributed embedded automation applications. It allows error recovery to be expressed in te...
Geert Deconinck, Vincenzo De Florio, Ronnie Belman...