CASES 2007 - PDF Preprint Papers

CASES 2007 International Conference on Compilers

Teaser Browsing | Click Here

Title Browsing | Click Here

Wall of Fame | Most Viewed CASES-2007 Paper

click to vote

CASES
2007
ACM

215views System Software» more CASES 2007»

Compiler generation from structural architecture descriptions

14 years 3 months ago

Download www.complang.tuwien.ac.at

With increasing complexity of modern embedded systems, the availability of highly optimizing compilers becomes more and more important. At the same time, application specific inst...

Florian Brandner, Dietmar Ebner, Andreas Krall

claim paper

Read More »

Disclaimer and Copyright Notice

Sciweavers respects the rights of all copyright holders and in this regard, authors are only allowed to share a link to their preprint paper on their own website. Every contribution is associated with a desciptive image. It is the sole responsibility of the authors to ensure that their posted image is not copyright infringing. This service is compliant with IEEE copyright.

Id	Views	Title	Status

1	215	Compiler generation from structural architecture descriptions	claim
2	209	An integrated ARM and multi-core DSP simulator	claim
3	205	INTACTE: an interconnect area, delay, and energy estimation tool for microarchitectural explorations	claim
4	181	A group-based wear-leveling algorithm for large-capacity flash memory storage systems	claim
5	179	Application driven embedded system design: a face recognition case study	claim
6	165	Performance evaluation and optimization of dual-port SDRAM architecture for mobile embedded systems	claim
7	165	Supporting multithreading in configurable soft processor cores	claim
8	163	Performance optimal processor throttling under thermal constraints	claim
9	158	A simplified java bytecode compilation system for resource-constrained embedded processors	claim
10	148	Hierarchical coarse-grained stream compilation for software defined radio	claim
11	145	A low power front-end for embedded processors using a block-aware instruction set	claim
12	144	Eliminating inter-process cache interference through cache reconfigurability for real-time and low-power embedded multi-tasking systems	claim
13	132	A fast and generic hybrid simulation approach using C virtual machine	claim
14	132	Fragment cache management for dynamic binary translators in embedded systems with scratchpad	claim
15	131	Cache leakage control mechanism for hard real-time systems	claim
16	124	Lightweight barrier-based parallelization support for non-cache-coherent MPSoC platforms	claim
17	119	Rethinking custom ISE identification: a new processor-agnostic method	claim
18	119	Recursive function data allocation to scratch-pad memory	claim
19	117	Stack size reduction of recursive programs	claim
20	116	Facilitating compiler optimizations through the dynamic mapping of alternate register structures	claim
21	115	A self-maintained memory module supporting DMM	claim
22	112	SCCP/x: a compilation profile to support testing and verification of optimized code	claim
23	112	An optimistic and conservative register assignment heuristic for chordal graphs	claim
24	110	Light-weight synchronization for inter-processor communication acceleration on embedded MPSoCs	claim
25	110	Towards understanding architectural tradeoffs in MEMS closed-loop feedback control	claim
26	109	A backtracking instruction scheduler using predicate-based code hoisting to fill delay slots	claim
27	97	Software controlled memory layout reorganization for irregular array access patterns	claim
28	94	Non-transparent debugging for software-pipelined loops	claim
29	89	Scratch-pad memory allocation without compiler support for java applications	claim
30	87	Performance-driven syntax-directed synthesis of asynchronous processors	claim
31	81	An efficient framework for dynamic reconfiguration of instruction-set customization	claim

Sciweavers

Explore & Download

Productivity Tools

Document Tools

Image Tools

Sciweavers