953 search results - page 172 / 191 » A Heuristic for Channel Routing |
FPL
2009
Springer
14 years 13 days ago
2009
Springer
Spatially-tiled architectures, such as Coarse-Grained Reconfigurable Arrays (CGRAs), are powerful architectures for accelerating applications in the digital-signal processing, em...
EMSOFT
2001
Springer
14 years 9 days ago
2001
Springer
The ability to incorporate low-power, wireless communication into embedded devices gives rise to a new genre of embedded software that is distributed, dynamic, and adaptive. This p...
ICPP
1999
IEEE
14 years 3 days ago
1999
IEEE
A router design for torus networks that significantly reduces message latency over traditional wormhole routers is presented in this paper. This new router implements virtual cut-...
EH
2004
IEEE
13 years 11 months ago
2004
IEEE
The work presented here tackles the problem of designing a unipolar 6-bit digital-to-analog converter (DAC) with a voltage mode output by hardware evolution. Thereby a Field Progr...
ASAP
2006
IEEE
13 years 9 months ago
2006
IEEE
Several semi-parallel decoding architectures have been explored by researchers for the quasi-cyclic low density parity check (LDPC) codes. In these architectures, the reconfigurab...