Sciweavers

469 search results - page 66 / 94
» A High Performance Exact Histogram Specification Algorithm
Sort
View
RECOMB
2005
Springer
14 years 9 months ago
Predicting Protein-Peptide Binding Affinity by Learning Peptide-Peptide Distance Functions
Many important cellular response mechanisms are activated when a peptide binds to an appropriate receptor. In the immune system, the recognition of pathogen peptides begins when th...
Chen Yanover, Tomer Hertz
SIGGRAPH
1994
ACM
14 years 1 months ago
Priority rendering with a virtual reality address recalculation pipeline
Virtual reality systems are placing never before seen demands on computer graphics hardware, yet few graphics systems are designed specifically for virtual reality. An address rec...
Matthew Regan, Ronald Pose
MICRO
2010
IEEE
202views Hardware» more  MICRO 2010»
13 years 3 months ago
Hardware Support for Relaxed Concurrency Control in Transactional Memory
Today's transactional memory systems implement the two-phase-locking (2PL) algorithm which aborts transactions every time a conflict happens. 2PL is a simple algorithm that pr...
Utku Aydonat, Tarek S. Abdelrahman
TCSV
2002
167views more  TCSV 2002»
13 years 8 months ago
Three-dimensional subband coding techniques for wireless video communications
This paper presents a new 3-D subband coding framework that is able to achieve a good balance between high compression performance and channel error resilience. Various data transf...
Hong Man, Ricardo L. de Queiroz, Mark J. T. Smith
VLSID
2009
IEEE
170views VLSI» more  VLSID 2009»
14 years 9 months ago
Code Transformations for TLB Power Reduction
The Translation Look-aside Buffer (TLB) is a very important part in the hardware support for virtual memory management implementation of high performance embedded systems. The TLB...
Reiley Jeyapaul, Sandeep Marathe, Aviral Shrivasta...