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» A High Performance Kernel-Less Operating System Architecture
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ICPADS
2006
IEEE
14 years 2 months ago
Loop Scheduling with Complete Memory Latency Hiding on Multi-core Architecture
The widening gap between processor and memory performance is the main bottleneck for modern computer systems to achieve high processor utilization. In this paper, we propose a new...
Chun Xue, Zili Shao, Meilin Liu, Mei Kang Qiu, Edw...
LCN
2006
IEEE
14 years 2 months ago
Performance Limits and Analysis of Contention-based IEEE 802.11 MAC
— Recent advance in IEEE 802.11 based standard has pushed the wireless bandwidth up to 600Mbps while keeping the same wireless medium access control (MAC) schemes for full backwa...
Shao-Cheng Wang, Ahmed Helmy
FPGA
2000
ACM
128views FPGA» more  FPGA 2000»
13 years 12 months ago
Factoring large numbers with programmable hardware
The fastest known algorithms for factoring large numbers share a core sieving technique. The sieving cores find numbers that are completely factored over a prime base set raised t...
Hea Joung Kim, William H. Mangione-Smith
SIPS
2008
IEEE
14 years 2 months ago
Efficient mapping of advanced signal processing algorithms on multi-processor architectures
Modern microprocessor technology is migrating from simply increasing clock speeds on a single processor to placing multiple processors on a die to increase throughput and power pe...
Bhavana B. Manjunath, Aaron S. Williams, Chaitali ...
SP
2003
IEEE
121views Security Privacy» more  SP 2003»
14 years 1 months ago
Specifying and Verifying Hardware for Tamper-Resistant Software
We specify a hardware architecture that supports tamper-resistant software by identifying an “idealized” hich gives the abstracted actions available to a single user program. ...
David Lie, John C. Mitchell, Chandramohan A. Thekk...