Factoring large numbers with programmable hardware

The fastest known algorithms for factoring large numbers share a core sieving technique. The sieving cores find numbers that are completely factored over a prime base set raised to some power. This sieving process dominates runtime for the range of numbers that are currently of interest, and it consumes an increasing fraction of runtime for the (currently) dominant algorithms as the range of numbers increases. This report presents a hardware architecture and implementation that improves the speed of the sieving process over current implementations. The architecture is based on programmable hardware connected to parallel memory banks, and achieves improved performance through highly concurrent execution by exploiting the unique properties of prime numbers. Currently, we have a functional sieving hardware on a single field-programmable gate array that operates at 16MHz with no optimizations. At 16MHz, we are able to achieve a speedup factor of 40 over an UltraSparc Workstation. Further ...

• Type: Conference
• Year: 2000
• Where: FPGA
• Authors: Hea Joung Kim, William H. Mangione-Smith
• Keywords: Core Sieving Technique, FPGA, FPGA 2000, Functional Sieving Hardware, Speedup Factor