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ECRTS
2005
IEEE
14 years 2 months ago
Cache Contents Selection for Statically-Locked Instruction Caches: An Algorithm Comparison
Cache memories have been extensively used to bridge the gap between high speed processors and relatively slower main memories. However, they are sources of predictability problems...
Antonio Martí Campoy, Isabelle Puaut, Angel...
HPCA
1999
IEEE
14 years 23 days ago
Impulse: Building a Smarter Memory Controller
Impulse is a new memory system architecture that adds two important features to a traditional memory controller. First, Impulse supports application-specific optimizations through...
John B. Carter, Wilson C. Hsieh, Leigh Stoller, Ma...
HIPEAC
2011
Springer
12 years 8 months ago
Decoupled zero-compressed memory
For each computer system generation, there are always applications or workloads for which the main memory size is the major limitation. On the other hand, in many cases, one could...
Julien Dusser, André Seznec
LCN
2006
IEEE
14 years 2 months ago
Minimizing Cache Misses in an Event-driven Network Server: A Case Study of TUX
We analyze the performance of CPU-bound network servers and demonstrate experimentally that the degradation in the performance of these servers under highconcurrency workloads is ...
Sapan Bhatia, Charles Consel, Julia L. Lawall
ESORICS
2002
Springer
14 years 8 months ago
Authentication for Distributed Web Caches
We consider the problem of offloading secure access-controlled content from central origin servers to distributed caches so clients can access a proximal cache rather than the orig...
James Giles, Reiner Sailer, Dinesh C. Verma, Sures...