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JPDC
2007
167views more  JPDC 2007»
13 years 8 months ago
On the design of high-performance algorithms for aligning multiple protein sequences on mesh-based multiprocessor architectures
In this paper, we address the problem of multiple sequence alignment (MSA) for handling very large number of proteins sequences on mesh-based multiprocessor architectures. As the ...
Diana H. P. Low, Bharadwaj Veeravalli, David A. Ba...
HIPC
2005
Springer
14 years 1 months ago
Preemption Adaptivity in Time-Published Queue-Based Spin Locks
Abstract. The proliferation of multiprocessor servers and multithreaded applications has increased the demand for high-performance synchronization. Traditional scheduler-based lock...
Bijun He, William N. Scherer III, Michael L. Scott
TC
2010
13 years 6 months ago
A Novel Weighted-Graph-Based Grouping Algorithm for Metadata Prefetching
— Although data prefetching algorithms have been extensively studied for years, there is no counterpart research done for metadata access performance. Existing data prefetching a...
Peng Gu, Jun Wang, Yifeng Zhu, Hong Jiang, Pengju ...
DATE
2009
IEEE
242views Hardware» more  DATE 2009»
14 years 2 months ago
A high performance reconfigurable Motion Estimation hardware architecture
Motion Estimation (ME) is the most computationally intensive part of video compression and video enhancement systems. For the recently available high definition frame sizes and hi...
Ozgur Tasdizen, Halil Kukner, Abdulkadir Akin, Ilk...
ICS
2007
Tsinghua U.
14 years 2 months ago
Cooperative cache partitioning for chip multiprocessors
This paper presents Cooperative Cache Partitioning (CCP) to allocate cache resources among threads concurrently running on CMPs. Unlike cache partitioning schemes that use a singl...
Jichuan Chang, Gurindar S. Sohi