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» A High-Performance Flexible Architecture for Cryptography
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FSE
2009
Springer
159views Cryptology» more  FSE 2009»
14 years 3 months ago
Intel's New AES Instructions for Enhanced Performance and Security
The Advanced Encryption Standard (AES) is the Federal Information Processing Standard for symmetric encryption. It is widely believed to be secure and efficient, and is therefore b...
Shay Gueron
FPGA
2004
ACM
158views FPGA» more  FPGA 2004»
14 years 1 months ago
A novel coarse-grain reconfigurable data-path for accelerating DSP kernels
In this paper, an efficient implementation of a high performance coarse-grain reconfigurable data-path on a mixed-granularity reconfigurable platform is presented. It consists of ...
Michalis D. Galanis, George Theodoridis, Spyros Tr...
ERSA
2007
177views Hardware» more  ERSA 2007»
13 years 10 months ago
Energy-Aware System Synthesis for Reconfigurable Chip Multiprocessors
- Even though state-of-the-art FPGAs present new opportunities in exploring low-cost high-performance architectures for floating-point scientific applications, they also pose serio...
Xiaofang Wang, Sotirios G. Ziavras, Jie Hu
SASN
2003
ACM
14 years 1 months ago
A security design for a general purpose, self-organizing, multihop ad hoc wireless network
We present a security design for a general purpose, selforganizing, multihop ad hoc wireless network, based on the IEEE 802.15.4 low-rate wireless personal area network standard. ...
Thomas S. Messerges, Johnas Cukier, Tom A. M. Keve...
FPGA
1999
ACM
174views FPGA» more  FPGA 1999»
14 years 21 days ago
Reduction of Latency and Resource Usage in Bit-Level Pipelined Data Paths for FPGAs
Pipelining of data path structures increases the throughput rate at the expense of enlarged resource usage and latency unless architectures optimized towards specific applications...
Peter Kollig, Bashir M. Al-Hashimi