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INFOCOM
2007
IEEE
14 years 2 months ago
Iterative Scheduling Algorithms
— The input-queued switch architecture is widely used in Internet routers due to its ability to run at very high line speeds. A central problem in designing an input-queued switc...
Mohsen Bayati, Balaji Prabhakar, Devavrat Shah, Ma...
PPOPP
2009
ACM
14 years 9 months ago
An efficient transactional memory algorithm for computing minimum spanning forest of sparse graphs
Due to power wall, memory wall, and ILP wall, we are facing the end of ever increasing single-threaded performance. For this reason, multicore and manycore processors are arising ...
Seunghwa Kang, David A. Bader
FPGA
2004
ACM
137views FPGA» more  FPGA 2004»
14 years 2 months ago
Multi-resource aware partitioning algorithms for FPGAs with heterogeneous resources
As FPGA densities increase, partitioning-based FPGA placement approaches are becoming increasingly important as they can be used to provide high-quality and computationally scalab...
Navaratnasothie Selvakkumaran, Abhishek Ranjan, Sa...
VLSID
2009
IEEE
170views VLSI» more  VLSID 2009»
14 years 9 months ago
Code Transformations for TLB Power Reduction
The Translation Look-aside Buffer (TLB) is a very important part in the hardware support for virtual memory management implementation of high performance embedded systems. The TLB...
Reiley Jeyapaul, Sandeep Marathe, Aviral Shrivasta...
FPGA
2009
ACM
233views FPGA» more  FPGA 2009»
14 years 3 months ago
FPCNA: a field programmable carbon nanotube array
Carbon nanotubes (CNTs), with their unique electronic properties, are promising materials for building nanoscale circuits. In this paper, we present a new CNT-based FPGA architect...
Chen Dong, Scott Chilstedt, Deming Chen