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IPPS
2007
IEEE
14 years 1 months ago
Rethinking Automated Synthesis of MPSoC Architectures
Emerging heterogeneous multiprocessors will have custom memory and bus architectures that must balance resource sharing and system partitioning to meet cost constraints. We propos...
Brett H. Meyer, Donald E. Thomas
LCN
2008
IEEE
14 years 1 months ago
DiCAP: Distributed Packet Capturing architecture for high-speed network links
— IP traffic measurements form the basis of several network management tasks, such as accounting, planning, intrusion detection, and charging. High-speed network links challenge ...
Cristian Morariu, Burkhard Stiller
FPGA
2008
ACM
136views FPGA» more  FPGA 2008»
13 years 9 months ago
A complexity-effective architecture for accelerating full-system multiprocessor simulations using FPGAs
Functional full-system simulators are powerful and versatile research tools for accelerating architectural exploration and advanced software development. Their main shortcoming is...
Eric S. Chung, Eriko Nurvitadhi, James C. Hoe, Bab...
JSS
2006
104views more  JSS 2006»
13 years 7 months ago
Modelling and simulation of off-chip communication architectures for high-speed packet processors
In this work, we propose a visual, custom-designed, event-driven interconnect simulation framework to evaluate the performance of off-chip multi-processor/memory communications ar...
Jacob Engel, Daniel Lacks, Taskin Koçak
IEEEHPCS
2010
13 years 6 months ago
Scalable instruction set simulator for thousand-core architectures running on GPGPUs
Simulators are still the primary tools for development and performance evaluation of applications running on massively parallel architectures. However, current virtual platforms a...
Shivani Raghav, Martino Ruggiero, David Atienza, C...