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ICCD
2006
IEEE
128views Hardware» more  ICCD 2006»
14 years 4 months ago
Polaris: A System-Level Roadmap for On-Chip Interconnection Networks
Technology trends are driving parallel on-chip architectures in the form of multi-processor systems-on-a-chip (MPSoCs) and chip multi-processors (CMPs). In these systems the incre...
Vassos Soteriou, Noel Eisley, Hangsheng Wang, Bin ...
ICCAD
2007
IEEE
137views Hardware» more  ICCAD 2007»
14 years 4 months ago
Analysis of large clock meshes via harmonic-weighted model order reduction and port sliding
— Clock meshes posses inherent low clock skews and excellent immunity to PVT variations, and have increasingly found their way to high-performance IC designs. However, analysis o...
Xiaoji Ye, Peng Li, Min Zhao, Rajendran Panda, Jia...
ICDCS
2010
IEEE
13 years 9 months ago
ASAP: Scalable Identification and Counting for Contactless RFID Systems
The growing importance of operations such as identification, location sensing and object tracking has led to increasing interests in contactless Radio Frequency Identification (RFI...
Chen Qian, Yunhuai Liu, Hoilun Ngan, Lionel M. Ni
IPPS
1999
IEEE
14 years 2 hour ago
Application of Parallel Processors to Real-Time Sensor Array Processing
Historically, most radar sensor array processing has been implemented using dedicated and specialized processing systems. This approach was necessary because the algorithm computa...
David R. Martinez
CLUSTER
2009
IEEE
14 years 13 days ago
A scalable and generic task scheduling system for communication libraries
Abstract—Since the advent of multi-core processors, the physionomy of typical clusters has dramatically evolved. This new massively multi-core era is a major change in architectu...
François Trahay, Alexandre Denis