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DATE
2000
IEEE
132views Hardware» more  DATE 2000»
14 years 4 days ago
A Generic Architecture for On-Chip Packet-Switched Interconnections
This paper presents an architectural study of a scalable system-level interconnection template. We explain why the shared bus, which is today's dominant template, will not me...
Pierre Guerrier, Alain Greiner
IPPS
2008
IEEE
14 years 2 months ago
Impact of multicores on large-scale molecular dynamics simulations
Processing nodes of the Cray XT and IBM Blue Gene Massively Parallel Processing (MPP) systems are composed of multiple execution units, sharing memory and network subsystems. Thes...
Sadaf R. Alam, Pratul K. Agarwal, Scott S. Hampton...
WETICE
2009
IEEE
14 years 2 months ago
Cloud Computing and the Lessons from the Past
— The skyrocketing demand for a new generation of cloud-based consumer and business applications is driving the need for next generation of datacenters that must be massively sca...
Rao Mikkilineni, Vijay Sarathy
ISPAN
2005
IEEE
14 years 1 months ago
A Scalable Method for Predicting Network Performance in Heterogeneous Clusters
An important requirement for the effective scheduling of parallel applications on large heterogeneous clusters is a current view of system resource availability. Maintaining such ...
Dimitrios Katramatos, Steve J. Chapin
HPCA
2009
IEEE
14 years 8 months ago
In-Network Snoop Ordering (INSO): Snoopy coherence on unordered interconnects
Realizing scalable cache coherence in the many-core era comes with a whole new set of constraints and opportunities. It is widely believed that multi-hop, unordered on-chip networ...
Niket Agarwal, Li-Shiuan Peh, Niraj K. Jha