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DATE
2000
IEEE

169views Hardware» more DATE 2000»

Transformational Placement and Synthesis

14 years 4 months ago

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Novel methodology and algorithms to seamlessly integrate logic synthesis and physical placement through a transformational approach are presented. Contrary to most placement algor...

Wilm E. Donath, Prabhakar Kudva, Leon Stok, Paul V...

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Id	Views	Title	Status

1	169	Transformational Placement and Synthesis	claim
2	142	Power and Delay Reduction via Simultaneous Logic and Placement Optimization in FPGAs	claim
3	140	Parallel and Distributed VHDL Simulation	claim
4	140	Resolution of Dynamic Memory Allocation and Pointers for the Behavioral Synthesis from C	claim
5	139	Target Architecture Oriented High-Level Synthesis for Multi-FPGA Based Emulation	claim
6	139	A VHDL Error Simulator for Functional Test Generation	claim
7	137	Retargeting of Compiled Simulators for Digital Signal Processors Using a Machine Description Language	claim
8	136	Smart Antenna Receiver Based on a Single Chip Solution for GSM/DCS Baseband Processing	claim
9	136	On Applying Incremental Satisfiability to Delay Fault Testing	claim
10	136	Parametric Fault Simulation and Test Vector Generation	claim
11	134	An on Chip ADC Test Structure	claim
12	132	Automatic Test Bench Generation for Validation of RT-Level Descriptions: An Industrial Experience	claim
13	132	A Generic Architecture for On-Chip Packet-Switched Interconnections	claim
14	130	Optimal Hardware Pattern Generation for Functional BIST	claim
15	129	Non-Linear Components for Mixed Circuits Analog Front-End	claim
16	128	A Bus Delay Reduction Technique Considering Crosstalk	claim
17	124	On the Generation of Multiplexer Circuits for Pass Transistor Logic	claim
18	121	Composite Signal Flow: A Computational Model Combining Events, Sampled Streams, and Vectors	claim
19	121	Functional Test Generation for Full Scan Circuits	claim
20	119	Bus Access Optimization for Distributed Embedded Systems Based on Schedulability Analysis	claim
21	117	Evaluating System Dependability in a Co-Design Framework	claim
22	116	An Object Oriented Design Method for Reconfigurable Computing Systems	claim
23	114	On Using Satisfiability-Based Pruning Techniques in Covering Algorithms	claim
24	114	Automating RT-Level Operand Isolation to Minimize Power Consumption in Datapaths	claim
25	113	MASCOT: A Specification and Cosimulation Method Integrating Data and Control Flow	claim
26	113	Static Timing Analysis of Embedded Software on Advanced Processor Architectures	claim
27	113	Built-In Generation of Weighted Test Sequences for Synchronous Sequential Circuits	claim
28	112	A Discrete-Time Battery Model for High-Level Power Estimation	claim
29	112	Quantitative Comparison of Power Management Algorithms	claim
30	112	The Road to Better Reliability and Yield Embedded DfM Tools	claim
31	111	Static Timing Analysis Taking Crosstalk into Account	claim
32	110	Stochastic Modeling and Performance Evaluation for Digital Clock and Data Recovery Circuits	claim
33	110	A BIST Scheme for On-Chip ADC and DAC Testing	claim
34	108	Automatic Abstraction for Worst-Case Analysis of Discrete Systems	claim
35	108	A 50 Mbit/s Iterative Turbo-Decoder	claim
36	105	System Synthesis for Multiprocessor Embedded Applications	claim
37	105	Technology Mapping and Retargeting for Field-Programmable Analog Arrays	claim
38	105	Yield Improvement and Repair Trade-Off for Large Embedded Memories	claim
39	103	Analysis of High-Level Address Code Transformations for Programmable Processors	claim
40	103	Protocol Stack-Based Telecom-Emulator	claim
41	101	Memory Arbitration and Cache Management in Stream-Based Systems	claim
42	100	A New Approach for Computation of Timing Jitter in Phase Locked Loops	claim
43	100	Delay-Insensitive Interface Specification and Synthesis	claim
44	99	CAS-BUS: A Scalable and Reconfigurable Test Access Mechanism for Systems on a Chip	claim
45	98	Automatic Lighthouse Generation for Directed State Space Search	claim
46	97	Layout-Oriented Synthesis of High Performance Analog Circuits	claim
47	95	Influence of Manufacturing Variations in IDDQ Measurements: A New Test Criterion	claim
48	95	Analyzing Real-Time Systems	claim
49	94	Shared Memory Implementations of Synchronous Dataflow Specifications	claim
50	93	Fast Evaluation of Sequence Pair in Block Placement by Longest Common Subsequence Computation	claim
51	93	Fast Hardware-Software Coverification by Optimistic Execution of Real Processor	claim
52	92	Standards for System-Level Design: Practical Reality or Solution in Search of a Question?	claim
53	92	An Efficient Heuristic Approach to Solve the Unate Covering Problem	claim
54	91	A Hierarchical Approach for the Symbolic Analysis of Large Analog Integrated Circuits	claim
55	90	Cost Reduction and Evaluation of a Temporary Faults Detecting Technique	claim
56	90	Fast Cache and Bus Power Estimation for Parameterized System-on-a-Chip Design	claim
57	89	Architectural Power Optimization by Bus Splitting	claim
58	89	A System-Level Synthesis Algorithm with Guaranteed Solution Quality	claim
59	88	Free MDD-Based Software Optimization Techniques for Embedded Systems	claim
60	88	Techniques for Reducing Read Latency of Core Bus Wrappers	claim
61	87	Multi-Node Static Logic Implications for Redundancy Identification	claim
62	87	Test Synthesis for Mixed-Signal SOC Paths	claim
63	86	A New Partitioning Method for Parallel Simulation of VLSI Circuits on Transistor Level	claim
64	86	Analysis and Minimization of Test Time in a Combined BIST and External Test Approach	claim
65	86	System Level Design Using C++	claim
66	85	Gate Sizing Using a Statistical Delay Model	claim
67	85	Alternative Test Methods Using IEEE 1149.4	claim
68	85	Meeting Delay Constraints in DSM by Minimal Repeater Insertion	claim
69	85	Assessing the Cost Effectiveness of Integrated Passives	claim
70	85	Stay Away from Minimum Design-Rule Values	claim
71	85	All Digital Built-in Delay and Crosstalk Measurement for On-Chip Buses	claim
72	83	Wave Steered FSMs	claim
73	83	A New IEEE 1149.1 Boundary Scan Design for the Detection of Delay Defects	claim
74	83	Predicting Coupled Noise in RC Circuits	claim
75	82	An Integrated Temporal Partitioning and Partial Reconfiguration Technique for Design Latency Improvement	claim
76	82	Constructive Library-Aware Synthesis Using Symmetries	claim
77	81	Abstraction from Counters: An Application on Real-Time Systems	claim
78	79	Logic Simulation Using Networks of State Machines	claim
79	79	Design and Test Space Exploration of Transport-Triggered Architectures	claim
80	78	HW/SW Codesign of an Engine Management System	claim
81	77	Designing Closer to the Edge	claim
82	76	Iterative Abstraction-Based CTL Model Checking	claim
83	75	Layout Compaction for Yield Optimization via Critical Area Minimization	claim
84	75	A New Effective And Efficient Multi-Level Partitioning Algorithm	claim
85	71	Clocktree RLC Extraction with Efficient Inductance Modeling	claim
86	71	A BDD-Based Satisfiability Infrastructure Using the Unate Recursive Paradigm	claim
87	71	Reducing the Complexity of Defect Level Modeling Using the Clustering Effect	claim
88	70	Faster Optimal Single-Row Placement with Fixed Ordering	claim
89	69	Detecting Undetectable Controller Faults Using Power Analysis	claim
90	69	Virtual Fault Simulation of Distributed IP-Based Designs	claim
91	66	Wire-Sizing for Delay Minimization and Ringing Control Using Transmission Line Model	claim
92	65	Test Quality and Fault Risk in Digital Filter Datapath BIST	claim
93	61	Cost and Benefit Models for Logic and Memory BIST	claim
94	61	Efficient Power Co-Estimation Techniques for System-on-Chip Design	claim
95	60	System Design Based on Single Language and Single-Chip Java ASIP Microcontroller	claim
96	56	Efficient Resource Arbitration in Reconfigurable Computing Environments	claim

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