Sciweavers

90 search results - page 10 / 18
» A Java Compiler for Many Memory Models
Sort
View
DATE
2004
IEEE
114views Hardware» more  DATE 2004»
14 years 24 days ago
Power Aware Variable Partitioning and Instruction Scheduling for Multiple Memory Banks
Many high-end DSP processors employ both multiple memory banks and heterogeneous register files to improve performance and power consumption. The complexity of such architectures ...
Zhong Wang, Xiaobo Sharon Hu
HPCA
1997
IEEE
14 years 1 months ago
Global Address Space, Non-Uniform Bandwidth: A Memory System Performance Characterization of Parallel Systems
Many parallel systems offer a simple view of memory: all storage cells are addresseduniformly. Despite a uniform view of the memory, the machines differsignificantly in theirmemo...
Thomas Stricker, Thomas R. Gross
ICASSP
2008
IEEE
14 years 3 months ago
Address assignment sensitive variable partitioning and scheduling for DSPS with multiple memory banks
Multiple memory banks design is employed in many high performance DSP processors. This architectural feature supports higher memory bandwidth by allowing multiple data memory acce...
Chun Jason Xue, Tiantian Liu, Zili Shao, Jingtong ...
ESOP
2010
Springer
14 years 6 months ago
Parameterized Memory Models and Concurrent Separation Logic
Formal reasoning about concurrent programs is usually done with the assumption that the underlying memory model is sequentially consistent, i.e. the execution outcome is equivalen...
Rodrigo Ferreira, Xinyu Feng and Zhong Shao
IPPS
2006
IEEE
14 years 3 months ago
Performance analysis of Java concurrent programming: a case study of video mining system
As multi/many core processors become prevalent, programming language is important in constructing efficient parallel applications. In this work, we build a multithreaded video min...
Wenlong Li, Eric Li, Ran Meng, Tao Wang, Carole Du...