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» A Java processor architecture for embedded real-time systems
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CODES
2005
IEEE
14 years 2 months ago
Power-smart system-on-chip architecture for embedded cryptosystems
In embedded cryptosystems, sensitive information can leak via timing, power, and electromagnetic channels. We introduce a novel power-smart system-on-chip architecture that provid...
Radu Muresan, Haleh Vahedi, Y. Zhanrong, Stefano G...
AINA
2007
IEEE
14 years 3 months ago
Sim-PowerCMP: A Detailed Simulator for Energy Consumption Analysis in Future Embedded CMP Architectures
Continuous improvements in integration scale have made major microprocessor vendors to move to designs that integrate several processor cores on the same chip. Chip-multiprocessor...
Antonio Flores, Juan L. Aragón, Manuel E. A...
PERCOM
2008
ACM
14 years 8 months ago
Estimating the Energy Consumption in Pervasive Java-Based Systems
We define and evaluate a framework for estimating the energy consumption of pervasive Java-based software systems. The framework's primary objective is to enable an engineer ...
Chiyoung Seo, Sam Malek, Nenad Medvidovic
ICES
2005
Springer
138views Hardware» more  ICES 2005»
14 years 2 months ago
A Flexible On-Chip Evolution System Implemented on a Xilinx Virtex-II Pro Device
Abstract. There have been introduced a number of systems with evolvable hardware on a single chip. To overcome the lack of flexibility in these systems, we propose a single-chip e...
Kyrre Glette, Jim Torresen
IPPS
2007
IEEE
14 years 3 months ago
A General Purpose Partially Reconfigurable Processor Simulator (PReProS)
An innovative technique to model and simulate partial and dynamic reconfigurable processors is presented in this paper. The basis for development is a SystemC kernel modified for ...
Alisson Vasconcelos De Brito, Matthias Kühnle...