19 search results - page 1 / 4 » A Large, Fast Instruction Window for Tolerating Cache Misses |
ISCA
2002
IEEE
14 years 3 months ago
2002
IEEE
Instruction window size is an important design parameter for many modern processors. Large instruction windows offer the potential advantage of exposing large amounts of instructi...
IPPS
2007
IEEE
14 years 5 months ago
2007
IEEE
This paper explores the correlation of instruction counts and cache misses to runtime performance for a large family of divide and conquer algorithms to compute the Walsh–Hadama...
ISPASS
2009
IEEE
14 years 5 months ago
2009
IEEE
Trace-driven simulation of superscalar processors is particularly complicated. The dynamic nature of superscalar processors combined with the static nature of traces can lead to l...
HPCA
2005
IEEE
14 years 11 months ago
2005
IEEE
The use of large instruction windows coupled with aggressive out-oforder and prefetching capabilities has provided significant improvements in processor performance. In this paper...
ALENEX
2003
14 years 7 days ago
2003
Ongoing changes in computer performance are affecting the efficiency of string sorting algorithms. The size of main memory in typical computers continues to grow, but memory acce...