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EURODAC
1994
IEEE
209views VHDL» more  EURODAC 1994»
13 years 11 months ago
MOS VLSI circuit simulation by hardware accelerator using semi-natural models
- The accelerator is destined to circuit-level simulation of digital and analog/digital MOS VLSI'c containing of up to 100 thousand transistors (with 16 Mb RAM host-machine). ...
Victor V. Denisenko
CASES
2007
ACM
13 years 11 months ago
Hierarchical coarse-grained stream compilation for software defined radio
Software Defined Radio (SDR) is an emerging embedded domain where the physical layer of wireless protocols is implemented in software rather than the traditional application speci...
Yuan Lin, Manjunath Kudlur, Scott A. Mahlke, Trevo...
CF
2007
ACM
13 years 11 months ago
Reconfigurable hybrid interconnection for static and dynamic scientific applications
As we enter the era of petascale computing, system architects must plan for machines composed of tens or even hundreds of thousands of processors. Although fully connected network...
Shoaib Kamil, Ali Pinar, Daniel Gunter, Michael Li...
FCCM
2004
IEEE
175views VLSI» more  FCCM 2004»
13 years 11 months ago
A Flexible Hardware Encoder for Low-Density Parity-Check Codes
We describe a flexible hardware encoder for regular and irregular low-density parity-check (LDPC) codes. Although LDPC codes achieve achieve better performance and lower decoding ...
Dong-U Lee, Wayne Luk, Connie Wang, Christopher Jo...
FOCS
2004
IEEE
13 years 11 months ago
Triangulation and Embedding Using Small Sets of Beacons
Concurrent with recent theoretical interest in the problem of metric embedding, a growing body of research in the networking community has studied the distance matrix defined by n...
Jon M. Kleinberg, Aleksandrs Slivkins, Tom Wexler